Techniques and configurations to impart strain to integrated circuit devices

ABSTRACT

Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a quantum well channel coupled with the semiconductor substrate, a source structure coupled with the quantum well channel, a drain structure coupled with the quantum well channel and a strain-inducing film disposed on and in direct contact with material of the source structure and the drain structure to reduce resistance of the quantum well channel by imparting a tensile or compressive strain on the quantum well channel, wherein the quantum well channel is disposed between the strain-inducing film and the semiconductor substrate. Other embodiments may be described and/or claimed.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to U.S. patent application Ser. No.12/646,697, entitled “TECHNIQUES AND CONFIGURATIONS TO IMPART STRAIN TOINTEGRATED CIRCUIT DEVICES,” filed Dec. 23, 2009. The application ishereby incorporated by reference herein in its entirety for allpurposes.

FIELD

Embodiments of the present disclosure generally relate to the field ofintegrated circuits, and more particularly, to techniques andconfigurations to impart strain to integrated circuit devices such ashorizontal field-effect transistors.

BACKGROUND

Generally, integrated circuit devices such as transistors are beingformed in emerging semiconductor thin films such as, for example, groupIII-V semiconductor materials for electronic or optoelectronic devices.Increasing carrier mobility of such group III-V materials may increase aspeed of integrated circuit devices formed therein.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be readily understood by the following detaileddescription in conjunction with the accompanying drawings. To facilitatethis description, like reference numerals designate like structuralelements. Embodiments are illustrated by way of example and not by wayof limitation in the figures of the accompanying drawings.

FIG. 1 schematically illustrates an example integrated circuit device inaccordance with some embodiments.

FIG. 2 provides a diagram of band gap energy and lattice constant forsome example semiconductor materials in accordance with someembodiments.

FIG. 3 provides a graph of stress and corresponding resistance for agroup III-V semiconductor material.

FIG. 4 provides a band gap energy diagram through a vertical directionof an integrated circuit device in accordance with some embodiments.

FIG. 5 schematically illustrates formation of a source structure anddrain structure in a semiconductor heterostructure after various processoperations in accordance with some embodiments.

FIG. 6 schematically illustrates formation of electrode structures and astrain-inducing film on a semiconductor heterostructure after variousprocess operations in accordance with some embodiments.

FIG. 7 is a flow diagram of a method for fabricating an integratedcircuit in accordance with some embodiments.

FIG. 8 schematically illustrates an example processor based system thatmay include an integrated circuit device as described herein inaccordance with some embodiments.

DETAILED DESCRIPTION

Embodiments of the present disclosure provide techniques andconfigurations to impart strain to integrated circuit devices such ashorizontal field effect transistors. In the following detaileddescription, reference is made to the accompanying drawings which form apart hereof wherein like numerals designate like parts throughout, andin which is shown by way of illustration embodiments which may bepracticed. It is to be understood that other embodiments may be utilizedand structural or logical changes may be made without departing from thescope of the present disclosure. Therefore, the following detaileddescription is not to be taken in a limiting sense, and the scope ofembodiments in accordance with the present disclosure is defined by theappended claims and their equivalents.

Various operations may be described as multiple discrete operations inturn, in a manner that is most helpful in understanding the claimedsubject matter. However, the order of description should not beconstrued as to imply that these operations are necessarily orderdependent. In particular, these operations may not be performed in theorder of presentation. Operations described may be performed in adifferent order than the described embodiment. Various additionaloperations may be performed and/or described operations may be omittedin additional embodiments.

The description may use perspective-based descriptions such ashorizontal/vertical, up/down, back/front, over/under, and top/bottom.Such descriptions may not restrict the application of embodimentsdescribed herein to a particular orientation.

For the purposes of the present disclosure, the phrase “A and/or B”means (A), (B), or (A and B). For the purposes of the presentdisclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B),(A and C), (B and C), or (A, B and C).

The description may use the phrases “in an embodiment,” or “inembodiments,” which may each refer to one or more of the same ordifferent embodiments. Furthermore, the terms “comprising,” “including,”“having,” and the like, as used with respect to embodiments of thepresent disclosure, are synonymous.

The term “coupled” may be used to describe various relationships betweencomponents herein. For example, the term “coupled to” may generallyrefer to a more direct physical connection between components, unlessotherwise expressed (e.g., “electrically coupled,” “communicativelycoupled,” or “coupled to [perform a function]”). The term “coupled with”generally refers to a physical connection where other interveningcomponents may or may not be present between such coupled components.

FIG. 1 schematically illustrates an example integrated circuit device inaccordance with some embodiments. In an embodiment, the integratedcircuit device 100 includes a semiconductor substrate 102, one or morebuffer films 104, a first barrier film 106, a quantum well channel 108,a second barrier film 110, an etch stop film 112, a contact film 114, asource structure 116, a drain structure 118, a source electrode 120, adrain electrode 122, a gate electrode 124, and a strain-inducing film126, coupled as shown.

The semiconductor substrate 102 may include N-type or P-type (100)off-oriented silicon, the crystalline directions of the semiconductorsubstrate 102 being symbolized by the convention (xyz), where x, y, andz represent respective crystallographic planes in three dimensions thatare perpendicular to one another. The semiconductor substrate 102 may,for example, include material of a (100) direction off-cut in a rangebetween about 2 degrees to about 8 degrees towards a (110) direction.Other off-cut orientations or a substrate 102 without an off-cutorientation may be used. Off-cutting may eliminate anti-phaseboundaries.

The semiconductor substrate 102 may have a high resistivity betweenabout 1 Ω-cm to about 50 kΩ-cm. High resistivity may allow for deviceisolation of one or more integrated circuit devices (e.g., integratedcircuit device 100) formed on an active surface 125 of the semiconductorsubstrate 102. The active surface 125 may be a substantially planarsurface upon which integrated circuit devices (e.g., integrated circuitdevice 100) such as transistors are formed.

One or more buffer films 104 may be coupled to the semiconductorsubstrate 102. In an embodiment, the one or more buffer films 104include a nucleation buffer film (not shown) and a graded buffer film(not shown). The nucleation buffer film may be used, for example, tofill semiconductor substrate 102 terraces with atomic bi-layers of asemiconductor material including, for example, one or more group III-Vsemiconductor materials and/or one or more group II-VI semiconductormaterials, or combinations thereof. A nucleation portion (not shown) ofthe nucleation buffer film may create a virtual polar semiconductorsubstrate 102. Such nucleation portion may, for example, have athickness of about 3 nanometers (nm) to about 50 nm. A buffer filmportion (not shown) of the nucleation buffer film may serve as a bufferagainst dislocation threading and/or provide control of a latticemismatch of about 4% to about 8% between the semiconductor substrate 102and the first barrier film 106. The buffer film portion of nucleationbuffer film may, for example, have a thickness of about 0.3 microns toabout 5 microns. The nucleation buffer film (e.g., the one or morebuffer films 104) may include group III-V semiconductors and/or groupII-VI semiconductors, such as gallium arsenide (GaAs). Other materialsystems may be used to form the nucleation buffer film including N-typeor P-type material systems.

The one or more buffer films 104 may further include a graded bufferfilm (not shown) formed on the nucleation buffer film (not shown). Thegraded buffer film may include, for example, group III-V semiconductormaterials and/or group II-VI semiconductor materials, or combinationsthereof. For example, the graded buffer film may include indium aluminumarsenide (In_(x)Al_(1−x)As), where x has a value between 0 and 1,representing the relative composition of the elements. In oneembodiment, x has a value between about 0 and about 0.52. In anotherembodiment, the graded buffer film includes indium aluminum antimonide(InAlSb).

Other material systems including N-type or P-type materials may be usedfor the graded buffer film in other embodiments. For example, the gradedbuffer film may include inverse graded InAlAs or indium gallium aluminumarsenide (InGaAlAs) to provide a larger bandgap for device isolation.Increasing the relative percentage of aluminum (Al) in the graded bufferfilm in such a material system may strategically increase strain (e.g.,compressive strain) to the quantum well channel 108 to increaseperformance of the integrated circuit device 100.

The graded buffer film may also provide stress relaxation between thesemiconductor substrate 102 and other lattice mismatched films, such as,for example, the first barrier film 106, to reduce threading dislocationdefects in the integrated circuit device 100. The graded buffer filmmay, for example, have a thickness of about 0.5 microns to 2 microns.Other thicknesses may be used in other embodiments. The one or morebuffer films 104 may include other buffer films, or techniques thatprovide similar function as described herein in other embodiments.

The one or more buffer films 104 may be epitaxially deposited. In anembodiment, the one or more buffer films are deposited by molecular beamepitaxy (MBE), atomic layer epitaxy (ALE), epitaxial growth, chemicalbeam epitaxy (CBE), metal-organic chemical vapor deposition (MOCVD), orcombinations thereof. Other suitable deposition methods may be used inother embodiments.

A first barrier film 106 may be coupled with the semiconductor substrate102. For example, the first barrier film 106 may be coupled to the oneor more buffer films 104 formed on the semiconductor substrate 102, asillustrated. The first barrier film 106 may include group III-Vsemiconductor materials and/or group II-VI semiconductor materials, orcombinations thereof. In an embodiment, the first barrier film 106includes indium aluminum arsenide (In_(x)Al_(1−x)As), where x has avalue between 0 and 1, representing the relative composition of theelements. According to various embodiments, x has a value between about0.5 and about 0.8. In another embodiment, the first barrier film 106includes indium aluminum antimonide (InAlSb). In yet another embodiment,the first barrier film 106 includes indium phosphide (InP). Othermaterial systems including N-type materials and/or P-type materials maybe used for the first barrier film 106 in other embodiments.

The first barrier film 106 may include a material that has a higherbandgap than a material used for the quantum well channel 108. Athickness for the first barrier film 106 may be selected to provide asufficient barrier to charge carriers in the quantum well channel 108.In an embodiment, the first barrier film 106 has a thickness of about 10nm to about 200 nm. Other thicknesses for the first barrier film 106 maybe used in other embodiments.

The first barrier film 106 may be epitaxially deposited. In anembodiment, the first barrier film 106 is deposited by molecular beamepitaxy (MBE), atomic layer epitaxy (ALE), epitaxial growth, chemicalbeam epitaxy (CBE), metal-organic chemical vapor deposition (MOCVD), orcombinations thereof. Other suitable deposition methods may be used inother embodiments.

A quantum well channel 108 may be coupled to the first barrier film 106.The quantum well channel 108 may include group III-V semiconductormaterials and/or group II-VI semiconductor materials, or combinationsthereof. In an embodiment, the quantum well channel 108 includes indiumgallium arsenide (In_(x)Ga_(1−x)As), where x has a value between 0 and1, representing the relative composition of the elements. In anembodiment, x includes values between about 0.5 and about 0.8. Inanother embodiment, the quantum well channel 108 includes indiumantimonide (InSb). The quantum well channel 108 may include variousother material systems including N-type or P-type materials in otherembodiments. The quantum well channel 108 provides a pathway for mobilecharge carriers such as electrons or holes to move between a sourcestructure 116 and a drain structure 118. According to variousembodiments, the quantum well channel 108 provides electron mobility forN-type devices and/or provides hole mobility for P-type devices.

According to various embodiments, the quantum well channel 108 has aband gap energy that is relatively smaller than a band gap for the firstbarrier film 106 and the second barrier film 110. The quantum wellchannel 108 may have a thickness that provides channel conductance forthe integrated circuit device 100. According to various embodiments, thequantum well channel 108 has a thickness of about 2 nm to about 15 nm.The quantum well channel 108 may have other thicknesses in otherembodiments.

The quantum well channel 108 may be epitaxially deposited. In anembodiment, the quantum well channel 108 is deposited by molecular beamepitaxy (MBE), atomic layer epitaxy (ALE), epitaxial growth, chemicalbeam epitaxy (CBE), metal-organic chemical vapor deposition (MOCVD), orcombinations thereof. Other suitable deposition methods may be used inother embodiments.

A source structure 116 is coupled to provide mobile charge carriers(e.g., electrons or holes) for the quantum well channel 108. Accordingto various embodiments, the source structure 116 includes a materialhaving a lattice constant that is different (e.g., greater or smaller)than a lattice constant of a material used to form the quantum wellchannel 108 to impart a strain on the quantum well channel 108. Thesource structure 116 may be epitaxially coupled to the quantum wellchannel 108 to form a heterojunction such that the different latticeconstant between the materials for the source structure 116 and thequantum well channel 108 creates a compressive or tensile strain on thequantum well channel 108. A material for the source structure 116 may beselected to provide a desired or sufficient conductivity and/orepitaxial connection with the quantum well channel 108 according towell-known band-gap engineering principles.

The source structure 116 may be coupled to horizontally inject themobile charge carriers into the quantum well channel 108. For example, astrain imparted by the source structure 116 may increase an injectionvelocity of the mobile charge carriers in a direction that issubstantially parallel with a direction (e.g., arrow 150) of currentflow in the quantum well channel 108. The direction indicated by arrow150 may be a longitudinal direction of the quantum well channel 108. Ahorizontal direction may refer to a direction (e.g., arrow 150) that issubstantially parallel with the active surface (e.g., 125) of thesemiconductor substrate 102 and/or substantially parallel with thelongitudinal direction of the quantum well channel 108. That is, strainimparted by the source structure 116 may be a uniaxial strain in adirection that is substantially parallel with the active surface (e.g.,125) of the semiconductor substrate and/or substantially parallel withthe longitudinal direction of the quantum well channel 108. According tovarious embodiments, the integrated circuit device 100 is a horizontalfield-effect transistor, or a high electron mobility transistor, orcombinations thereof. The integrated circuit device 100 may includeother types of transistors that benefit from embodiments describedherein, including non-planar transistors such as multi-gate transistors.The integrated circuit device 100 may be a transistor having a gatelength of about 15 nm. Other gate lengths may be used in otherembodiments.

Applying a strain to the quantum well channel 108 as described hereinmay reduce an effective mass and/or resistance of the quantum wellchannel 108, thereby increasing a velocity of mobile charge carriers inthe quantum well channel 108. Increasing the velocity of the mobilecharge carriers may improve direct current (DC) and radio frequency (RF)characteristics of the integrated circuit device 100.

The source structure 116 may be formed using a variety of materialsincluding group III-V semiconductor materials and/or group II-VIsemiconductor materials, or combinations thereof. In an embodiment, thesource structure 116 includes gallium arsenide (GaAs). In anotherembodiment, the source structure 116 includes indium aluminum arsenide(InAlAs). According to various embodiments, the source structure 116 hasa thickness of less than about 60 nm. The source structure 116 may haveother thicknesses in other embodiments. In an embodiment, the sourcestructure 116 is deposited by molecular beam epitaxy (MBE), atomic layerepitaxy (ALE), epitaxial growth, chemical beam epitaxy (CBE),metal-organic chemical vapor deposition (MOCVD), or combinationsthereof. Other suitable deposition methods may be used in otherembodiments.

A drain structure 118 may be coupled to receive the mobile chargecarriers from the quantum well channel 108. According to variousembodiments, the drain structure 118 includes a material having alattice constant that is different (e.g., greater or smaller) than alattice constant of a material used to form the quantum well channel 108to impart a strain on the quantum well channel 108. The drain structure118 may be epitaxially coupled to the quantum well channel 108 to form aheterojunction such that the different lattice constant between thematerials for the drain structure 118 and the quantum well channel 108creates a compressive or tensile strain on the quantum well channel 108.A material for the drain structure 118 may be selected to provide adesired or sufficient conductivity and/or epitaxial connection with thequantum well channel 108 according to well-known band-gap engineeringprinciples.

According to various embodiments, the drain structure 118 includes thesame material as the source structure 116 to conjunctively increase orenhance the compressive or tensile strain applied to the quantum wellchannel 108 by the source structure 116. In an embodiment, a latticeconstant for a material used to form the source structure 116 and/or thedrain structure 118 is smaller than a lattice constant for a materialused to form the quantum well channel 108 to impart a tensile strainthat increases a velocity of electrons in an N-type integrated circuitdevice. In another embodiment, a lattice constant for a material used toform the source structure 116 and/or the drain structure 118 is largerthan a lattice constant for a material used to form the quantum wellchannel 108 to impart a compressive strain that increases a velocity ofholes in a P-type integrated circuit device.

The drain structure 118 may be formed using a variety of materialsincluding group III-V semiconductor materials and/or group II-VIsemiconductor materials, or combinations thereof. In an embodiment, thedrain structure 118 includes gallium arsenide (GaAs). In anotherembodiment, the drain structure 118 includes indium aluminum arsenide(InAlAs). According to various embodiments, the drain structure 118 hasa thickness of less than about 60 nm. The drain structure 118 may haveother thicknesses in other embodiments. In an embodiment, the drainstructure 118 is deposited by molecular beam epitaxy (MBE), atomic layerepitaxy (ALE), epitaxial growth, chemical beam epitaxy (CBE),metal-organic chemical vapor deposition (MOCVD), or combinationsthereof. Other suitable deposition methods may be used in otherembodiments.

The source structure 116 and/or the drain structure 118 may be dopedwith an impurity, according to various embodiments. For example, thesource structure 116 and/or the drain structure 118 may be delta-doped,modulation doped and/or combinations thereof. For an N-type device, thesource structure 116 and/or the drain structure 118 may be doped withsilicon (Si), sulfur (S), tellurium (Te), or combinations thereof. For aP-type device, the source structure 116 and/or the drain structure 118may be doped with beryllium (Be), carbon (C), or combinations thereof.Other impurities may be used to dope the source structure 116 and/or thedrain structure 118 in other embodiments. According to one or moreembodiments, the quantum well channel 108 may be un-doped while thesource structure 116 and/or the drain structure 118 are doped to createan N-type or P-type device. In such embodiment, the undoped quantumwell-channel 108 may be a channel of the N-type or P-type device.

A second barrier film 110 may be coupled to the quantum well channel 108to provide confinement for mobile charge carriers when they travel inthe quantum well channel 108. The second barrier film 110 may comportwith embodiments already described in connection with the first barrierfilm 110 including material types, thicknesses, and/or depositiontechniques. According to various embodiments, the second barrier film110 is a Schottky barrier layer for control of the quantum well channel108 using the gate electrode 124. In an embodiment, the quantum wellchannel 108 is disposed between the first barrier film 110 and thesecond barrier film 110, as illustrated.

An etch stop film 112 may be coupled with the second barrier film 110.The etch stop film 112 may be used to facilitate formation of the gateelectrode 124. The etch stop film 112 may include group III-Vsemiconductor materials and/or group II-VI semiconductor materials, orcombinations thereof, including, for example, indium phosphide (InP),InAlSb, or suitable combinations thereof. Other material systemsincluding N-type materials and/or P-type materials may be used for theetch stop film 112 in other embodiments.

In an embodiment, the etch stop film 112 has a thickness of about 2 nmto 15 nm. Other thicknesses for the etch stop film 112 may be used inother embodiments. In an embodiment, the etch stop film 112 is depositedby molecular beam epitaxy (MBE), atomic layer epitaxy (ALE), epitaxialgrowth, chemical beam epitaxy (CBE), metal-organic chemical vapordeposition (MOCVD), or combinations thereof. Other suitable depositionmethods may be used in other embodiments.

A contact film 114 may be coupled with the etch stop film 112. Thecontact film 114 may include group III-V semiconductor materials and/orgroup II-VI semiconductor materials, or combinations thereof, including,for example, InGaAs. Other material systems including N-type materialsand/or P-type materials may be used for the contact film 114 in otherembodiments. The contact film 114 may be doped to increase electricalconductivity of the contact film 114. For example, the contact film 114may be delta-doped, modulation doped and/or combinations thereof. For anN-type device, the contact film 114 may be doped with silicon (Si),sulfur (S), tellurium (Te), or combinations thereof. For a P-typedevice, the contact film 114 may be doped with beryllium (Be), carbon(C), or combinations thereof. Other impurities may be used to dope thecontact film 114 in other embodiments. Other structures described hereinmay be doped according to similar principles to affect conductivity orother physical or electrical properties.

In an embodiment, the contact film 114 has a thickness of about 5 to 50nm. Other thicknesses of the contact film 114 may be used in otherembodiments. In an embodiment, the contact film 114 is deposited bymolecular beam epitaxy (MBE), atomic layer epitaxy (ALE), epitaxialgrowth, chemical beam epitaxy (CBE), metal-organic chemical vapordeposition (MOCVD), or combinations thereof. Other suitable depositionmethods may be used in other embodiments. The integrated circuit device100 may include other films and structures such as, for example, spacerfilms, doped films, other barrier films, and/or strain-inducing films,which may intervene between structures and features described herein,according to various embodiments.

A source electrode 120 and a drain electrode 122 may be coupled to therespective source structure 116 and the drain structure 122. A gateelectrode 124 may be coupled to control the flow of mobile chargecarriers in the quantum well channel 108. According to variousembodiments, a gate dielectric (not shown) may be formed between thegate electrode 124 and the quantum well channel 108. The gate dielectricmay include, for example silicon oxide (SiO₂), silicon oxynitride(SiO_(x)N_(y)), silicon nitride (Si_(x)N_(y)) aluminum oxide (Al₂O₃),hafnium oxide (HfO₂), hafnium aluminum oxide (HfAl_(x)O_(y)), hafniumsilicon oxide (HfSi_(x)O_(y)), zirconium oxide (ZrO₂), zirconium siliconoxide (ZrSi_(x)O_(y)), lanthanum oxide (La₂O₃), yttrium oxide (Y₂O₃),lanthanum aluminum oxide (LaAl_(x)O_(y)), tantalum oxide (Ta₂O₅),titanium oxide (TiO₂), barium strontium titanium oxide(BaSrTi_(x)O_(y)), barium titanium oxide (BaTi_(x)O_(y)), strontiumtitanium oxide (SrTi_(x)O_(y)), lead scandium tantalum oxide(PbSc_(x)Ta_(y)O_(z)), or lead zinc niobate (PbZn_(x)Nb_(y)O_(z)), orcombinations thereof, where x, y, and z represent suitable quantities ofthe respective elements. Other materials may be used in otherembodiments for the gate dielectric.

The contact film 114 may be electrically insulated or isolated from thegate electrode 124 by a variety of techniques, including, for example,recessing the contact film 114 to form an air gap or depositing a spacerdielectric material between the gate electrode 124 and the contact film114. In an embodiment, the second barrier film 110 is a Schottky barrierlayer for the gate electrode 124 to provide a Schottky junction throughwhich the gate electrode 124 may control the quantum well channel 108.

The gate electrode 124, the source electrode 120, and the drainelectrode 122 may include a wide variety of suitable electricallyconductive materials. For example, the electrodes 120, 122, 124 mayinclude copper (Cu), gold (Au), tungsten (W), titanium (Ti), tantalum(Ta), platinum (Pt), nickel (Ni), cobalt (Co), rhodium (Rh), ruthenium(Ru), palladium (Pd), hafnium (Hf), zirconium (Zr), or aluminum (Al), orcombinations thereof. The electrodes 120, 122, 124 may include a metalnitride such as, for example, titanium nitride (TiN), tungsten nitride(WN), or tantalum nitride (TaN), or combinations thereof. The electrodes120, 122, 124 may include a metal silicide such as, for example,titanium silicide (TiSi), tungsten silicide (WSi), tantalum silicide(TaSi), cobalt silicide (CoSi), platinum silicide (PtSi), nickelsilicide (NiSi), or combinations thereof. The electrodes 120, 122, 124may include a metal silicon nitride such as, for example, titaniumsilicon nitride (TiSiN), or tantalum silicon nitride (TaSiN), orcombinations thereof. The electrodes 120, 122, 124 may include a metalcarbide such as, for example, titanium carbide (TiC), zirconium carbide(ZrC), tantalum carbide (TaC), hafnium carbide (HfC), or aluminumcarbide (AIC), or combinations thereof. The electrodes 120, 122, 124 mayinclude a metal carbon nitride such as, for example, tantalum carbonnitride (TaCN), titanium carbon nitride (TiCN), or combinations thereof.Other suitable materials may be used in other embodiments for theelectrodes 120, 122, 124 such as conductive metal oxides (e.g.,ruthenium oxide).

A strain-inducing film 126 may be formed on or over the electrodes120,122, 124 and/or the contact film 114, the source structure 116, andthe drain structure 118. According to various embodiments, thestrain-inducing film 126 is an amorphous material that isblanket-deposited (e.g., deposited over and on all exposed structures ofthe integrated circuit device 100) by any of a variety of well-knowndeposition techniques to stress the deposited material such asplasma-enhanced chemical vapor deposition (PECVD) and/or low pressurechemical vapor deposition (LPCVD). Portions of the strain-inducing film126 may be recessed or selectively removed to allow formation ofconductive interconnects to be coupled with the electrodes 120, 122,124. In the process of relaxing, the strain-inducing film 126 maytransfer strain to underlying structures such as the quantum channel 108of the integrated circuit device 100. According to various embodiments,the strain may be compressive for P-type integrated circuit devices ortensile for N-type integrated circuit devices. The strain-inducing film126 may incorporate a variety of materials including, for example,silicon nitride or silicon oxide materials. In an embodiment, thestrain-inducing film 126 has a thickness of about 10 nm. Otherthicknesses may be used in other embodiments.

FIG. 2 provides a diagram 200 of band gap energy and lattice constantfor some example semiconductor materials in accordance with someembodiments. The band gap energy (eV) is depicted on a vertical axis 202and a lattice constant (Angstroms) is depicted on a horizontal axis 204.The diagram 200 depicts some example semiconductor materials that may beused to fabricate the integrated circuit device 100 for visualcomparison of respective band gap energies and lattice constants. Forexample, points are illustrated on the diagram 200 for indium antimonide(InSb), indium arsenide (InAs), indium gallium arsenide (InGaAs),germanium (Ge), gallium antimonide (GaSb), silicon (Si), indiumphosphide (InP), gallium arsenide (GaAs), aluminum antimonide (AlSb),aluminum arsenide (AlAs), gallium phosphide (GaP), and aluminumphosphide (AlP). Materials for structures and features described hereinmay be selected to provide a desired or sufficient conductivity and/orepitaxial connection relative to adjacent structures and featuresaccording to well-known band-gap engineering principles.

The example semiconductor materials depicted in the diagram 200 are notintended to be an exhaustive representation of materials that can beused to form structures described herein. A wide variety of suitablematerials, many of which may not be illustrated in the diagram 200, canbe used to form structures described herein, including othercombinations of the elements and compounds depicted in diagram 200.

FIG. 3 provides a graph 300 of stress and corresponding resistance for agroup III-V semiconductor material. A horizontal axis 302 depicts stressin megapascals (MPa) and a vertical axis 304 depicts a change ofresistance (Rs) in percentage (%) for an applied stress. The points 306correspond with data collected from bending a wafer including indiumgallium arsenide (InGaAs) to impart stress (e.g., longitudinal tensionto spread atoms apart in a direction of current flow) on the InGaAs. Thetrend line 308 is a best fit line through the data points 306. The trendline 308 shows a general decrease in resistance (e.g., sheet resistance)with increasing stress, which may provide increased mobility of chargecarriers in an N-type device.

FIG. 4 provides a band gap energy diagram 400 through a verticaldirection (e.g., from A to A′) of the integrated circuit device 100. Ahorizontal axis 402 represents vertical position through the integratedcircuit device 100 in nanometers (nm) and vertical axis 404 representsincreasing energy in electron-volts (eV) in the direction of thevertical axis arrow. A valence band energy 406 and a conduction bandenergy 408 for materials between position A and position A′ of theintegrated circuit device 100 are depicted. As illustrated, a band gapenergy 410 of the second barrier film (e.g., 110) is greater than a bandgap energy 412 of the quantum well channel (e.g., 108) and a band gapenergy 414 of the first barrier film (e.g., 106) is greater than theband gap energy 412 of the quantum well channel (e.g., 108). The firstbarrier film (e.g., 106) and the second barrier film (e.g., 110) may bedoped with an impurity to provide confinement of mobile charge carriersto the quantum well channel (e.g., 108).

FIG. 5 schematically illustrates formation of a source structure 516 anddrain structure 518 in a semiconductor heterostructure 500 a aftervarious process operations in accordance with some embodiments. Asemiconductor heterostructure 500 a may be formed according to varioustechniques described herein. A first barrier film 506 may be formed andcoupled with a semiconductor substrate 502. For example, the firstbarrier film 506 may be deposited on the semiconductor substrate 502 oron one or more buffer films (e.g., 104) formed on the semiconductorsubstrate 502.

A material for quantum well channel 508 may be deposited on or over thefirst barrier film 506, followed by deposition of a material for thesecond barrier film 510 on or over the quantum well channel 508. Acontact film 514 may be deposited on or over the second barrier film 510to form the semiconductor heterostructure 500 a. The semiconductorheterostructure 500 a may include other films and/or structures,including films described herein (e.g., etch stop film 112 of theintegrated circuit device 100), that are omitted in FIG. 5 for the sakeof clarity. The films 506, 510, 514, and the quantum well channel 508may be epitaxially deposited.

In manufacturing product 500 b, portions of the semiconductorheterostructure 500 a are selectively removed to form a first recessedregion 515 and a second recessed region 517. In an embodiment, portionsof at least the contact film 514, the second barrier film 510, and thequantum well channel 508 are removed to form the first recessed region515 and the second recessed region 517. In another embodiment, portionsof the semiconductor heterostructure 500 a are selectively removed priorto deposition of the contact film 514. In such embodiment, portions ofat least the second barrier film 510 and the quantum channel 508 areremoved to form the first recessed region 515. The contact film 514 maybe subsequently deposited subsequent to formation of the first recessedregion 515 and/or the second recessed region 517 according to variousembodiments.

In an embodiment, the first recessed region 515 and the second recessedregion 517 are simultaneously formed by an etching process. The firstrecessed region 515 and the second recessed region 517 may be separatelyformed in other embodiments. Other processes such as lithography orother patterning processes may be used to selectively remove portions ofthe semiconductor heterostructure 500 a to form the first recessedregion 515 and the second recessed region 517 in the manufacturingproduct 500 b.

In manufacturing product 500 c, a material is deposited to form a sourcestructure 516 in the first recessed region 515 and a drain structure 518in the second recessed region 517. The material of the source structure516 and the drain structure 518 may have a lattice constant that islarger or smaller than a lattice constant of the material used to formthe quantum well channel 508. According to various embodiments, materialfor the source structure 516 and the drain structure 518 issimultaneously deposited. The source structure 516 and the drainstructure 518 may be separately formed in other embodiments. Materialfor the source structure 516 and/or the drain structure may beepitaxially deposited. The source structure 516 and the drain structure518 may apply uniaxial strain (e.g., compressive or tensile) to thequantum well channel 508 according to techniques described herein toincrease velocity of mobile charge carriers in an integrated circuitdevice (e.g., 100).

FIG. 6 schematically illustrates formation of electrode structures(e.g., 620, 622, 624) and a strain-inducing film (e.g., 626) on asemiconductor heterostructure (e.g., 500 a) after various processoperations in accordance with some embodiments. Manufacturing product600 a represents the manufacturing product 500 c of FIG. 5 afterformation of a source electrode 620, a drain electrode 622, and a gateelectrode 624.

In manufacturing product 600 a, the gate electrode 624 may be formed byselective removal (e.g., by etching and/or lithography) of portions ofat least the contact film 514 and the second barrier film 510 to form athird recessed region (not shown). An etch stop film (e.g., 112) may beused to facilitate control of etching processes to form the thirdrecessed region. A gate dielectric (not shown) may be deposited into thethird recessed region, and a material to form the gate electrode 624 maybe deposited on the gate dielectric. The contact film 514 may berecessed to electrically insulate the gate electrode 624 from thecontact film 514 or to reduce leakage from the gate electrode 624 to thecontact film 514. Gate electrode 624 may be electrically insulated fromconductive elements (e.g., the contact film 514) in a variety of waysincluding by an air spacer, an insulating material such as silicon oxideor silicon nitride, or a high-k dielectric to line the sidewalls of thecontact film 514. Other gate control techniques and structures may beused in other embodiments. For example, the second barrier film 510 mayoperate as a Schottky junction for control of the quantum well channel508.

An electrode material may be deposited to form the source electrode 620and the drain electrode 622. A variety of suitable deposition techniquesincluding chemical vapor deposition, sputtering, and/or epitaxialdeposition techniques may be used to deposit the electrodes 620, 622,624. Patterning techniques such as lithography and/or etch processes maybe used to selectively deposit the electrode material. In an embodiment,electrode material for the source electrode 620, the drain electrode622, and the gate electrode 624 is deposited during the same depositionoperation. In other embodiments, one or more of the electrodes 620, 622,624 are formed during separate deposition operations.

In manufacturing product 600 b, a strain-inducing film 626 is formed onor over the manufacturing product 600 a. The strain-inducing film 626may be deposited according to a variety of techniques to impart strainon the underlying structures, such as the quantum well channel 508,including, for example, plasma-enhanced chemical vapor deposition(PECVD) and/or low pressure chemical vapor deposition (LPCVD) methods tostress the material deposited to form the strain-inducing film 626.Portions of the strain-inducing film 626 may be recessed or selectivelyremoved to allow formation of conductive interconnects to be coupledwith the electrodes 620, 622, 624. According to various embodiments, thestrain may be compressive for P-type integrated circuit devices ortensile for N-type integrated circuit devices. The strain-inducing film626 may incorporate a variety of materials including, for example,silicon nitride or silicon oxide materials. In an embodiment, thestrain-inducing film 626 has a thickness of about 10 nm. Otherthicknesses may be used in other embodiments. Other well-knownsemiconductor structures and/or process operations may be used infabricating the manufacturing product 600 b.

FIG. 7 is a flow diagram of a method 700 for fabricating an integratedcircuit (e.g., 100) in accordance with some embodiments. The method 700includes forming a semiconductor heterostructure at block 702. Thesemiconductor heterostructure (e.g., 500 a) can be formed according to avariety of techniques described herein. In an embodiment, thesemiconductor heterostructure is formed by depositing a first barrierfilm on or over a semiconductor substrate, depositing a quantum wellchannel film on or over the first barrier film, depositing a secondbarrier film on or over the quantum well channel film, and/or depositinga contact film on or over the second barrier film. Other interveningfilms and/or structures may be deposited to form the semiconductorheterostructure. The films may be epitaxially deposited according tovarious embodiments.

At block 704, the method 700 further includes selectively removingportions of the semiconductor heterostructure to form a first recessedregion and a second recessed region in the semiconductorheterostructure. For example, portions of the contact film, the secondbarrier film and/or the quantum well channel may be selectively removed.The selective removal may be performed by etch and/or lithographyprocesses.

At block 706, the method 700 further includes depositing a material toform a source and a drain structure in the first recessed region and thesecond recessed region. The material used to form the source structureand the drain structure may be the same. In such case, the material maybe deposited during the same deposition operation to form the sourcestructure and the drain structure.

At block 708, the method 700 further includes forming electrodestructures (e.g., 620, 622, 624) for the source structure, the drainstructure, and a gate structure to form a transistor device (e.g., 100or 600 a). At block 710, the method 700 further includes depositing astrain-inducing film (e.g., 126 or 626) on the transistor device toreduce resistance in a quantum well channel (e.g., 108 or 508) of thetransistor device. Method 700 may include other techniques andconfigurations described in connection with FIGS. 1-6.

FIG. 8 schematically illustrates an example processor based system 2000that may include an integrated circuit device (e.g., 100) as describedherein in accordance with some embodiments. The processor system 2000may be a desktop computer, a laptop computer, a handheld computer, atablet computer, a PDA, a server, an Internet appliance, and/or anyother type of computing device.

The processor system 2000 illustrated in FIG. 8 includes a chipset 2010,which includes a memory controller 2012 and an input/output (I/O)controller 2014. The chipset 2010 may provide memory and I/O managementfunctions as well as a plurality of general purpose and/or specialpurpose registers, timers, etc. that are accessible or used by aprocessor 2020. The processor 2020 may be implemented using one or moreprocessors, WLAN components, WMAN components, WWAN components, and/orother suitable processing components. The processor 2020 may include acache 2022, which may be implemented using a first-level unified cache(L1), a second-level unified cache (L2), a third-level unified cache(L3), and/or any other suitable structures to store data.

The memory controller 2012 may perform functions that enable theprocessor 2020 to access and communicate with a main memory 2030including a volatile memory 2032 and a non-volatile memory 2034 via abus 2040. While FIG. 8 shows a bus 2040 to communicatively couplevarious components to one another, other embodiments may includeadditional/alternative interfaces.

The volatile memory 2032 may be implemented by synchronous dynamicrandom access memory (SDRAM), dynamic random access memory (DRAM),RAMBUS dynamic random access memory (RDRAM), and/or any other type ofrandom access memory device. The non-volatile memory 2034 may beimplemented using flash memory, read only memory (ROM), electricallyerasable programmable read only memory (EEPROM), and/or any otherdesired type of memory device.

The processor system 2000 may also include an interface circuit 2050that is coupled to the bus 2040. The interface circuit 2050 may beimplemented using any type of interface standard such as an Ethernetinterface, a universal serial bus (USB), a third generation input/outputinterface (3GIO) interface, and/or any other suitable type of interface.

One or more input devices 2060 may be connected to the interface circuit2050. The input device(s) 2060 permit an individual to enter data andcommands into the processor 2020. For example, the input device(s) 2060may be implemented by a keyboard, a mouse, a touch-sensitive display, atrack pad, a track ball, an isopoint, and/or a voice recognition system.

One or more output devices 2070 may also be connected to the interfacecircuit 2050. For example, the output device(s) 2070 may be implementedby display devices (e.g., a light emitting display (LED), a liquidcrystal display (LCD), a cathode ray tube (CRT) display, a printerand/or speakers). The interface circuit 2050 may include, among otherthings, a graphics driver card.

The processor system 2000 may also include one or more mass storagedevices 2080 to store software and data. Examples of such mass storagedevice(s) 2080 include floppy disks and drives, hard disk drives,compact disks and drives, and digital versatile disks (DVD) and drives.

The interface circuit 2050 may also include a communication device suchas a modem or a network interface card to facilitate exchange of datawith external computers via a network. The communication link betweenthe processor system 2000 and the network may be any type of networkconnection such as an Ethernet connection, a digital subscriber line(DSL), a telephone line, a cellular telephone system, a coaxial cable,etc.

In some embodiments, the processor system 2000 may be coupled to anantenna structure (not shown in the figure) to provide access to otherdevices of a network. In some embodiments, the antenna structure mayinclude one or more directional antennas, which radiate or receiveprimarily in one direction (e.g., for 120 degrees), cooperativelycoupled to one another to provide substantially omnidirectionalcoverage; or one or more omnidirectional antennas, which radiate orreceive equally well in all directions. In some embodiments, the antennastructure may include one or more directional and/or omnidirectionalantennas, including, e.g., a dipole antenna, a monopole antenna, a patchantenna, a loop antenna, a microstrip antenna or any other type ofantennas suitable for OTA transmission/reception of RF signals.

Access to the input device(s) 2060, the output device(s) 2070, the massstorage device(s) 2080 and/or the network may be controlled by the I/Ocontroller 2014. In particular, the I/O controller 2014 may performfunctions that enable the processor 2020 to communicate with the inputdevice(s) 2060, the output device(s) 2070, the mass storage device(s)2080 and/or the network via the bus 2040 and the interface circuit 2050.

While the components shown in FIG. 8 are depicted as separate blockswithin the processor system 2000, the functions performed by some ofthese blocks may be integrated within a single semiconductor circuit ormay be implemented using two or more separate integrated circuits. Forexample, although the memory controller 2012 and the I/O controller 2014are depicted as separate blocks within the chipset 2010, the memorycontroller 2012 and the I/O controller 2014 may be integrated within asingle semiconductor circuit.

According to various embodiments, the processor 2020, the main memory2030, or the chipset 2010, or combinations thereof, may include one ormore integrated circuit devices (e.g., 100) or transistors that includefeatures described herein. The one or more integrated circuit devicesmay include, for example, horizontal field-effect transistors, or highelectron mobility transistors (HEMT), or combinations thereof. Theprocessor 2020, the main memory 2030, or the chipset 2010 may include aP-type metal-oxide-semiconductor (PMOS) device and/or an N-typemetal-oxide-semiconductor (NMOS) device.

Although certain embodiments have been illustrated and described hereinfor purposes of description, a wide variety of alternate and/orequivalent embodiments or implementations calculated to achieve the samepurposes may be substituted for the embodiments shown and describedwithout departing from the scope of the present disclosure. Thisapplication is intended to cover any adaptations or variations of theembodiments discussed herein. Therefore, it is manifestly intended thatembodiments described herein be limited only by the claims and theequivalents thereof.

What is claimed is:
 1. An apparatus comprising: a semiconductorsubstrate; a quantum well channel coupled with the semiconductorsubstrate; a source structure coupled with the quantum well channel; adrain structure coupled with the quantum well channel; and astrain-inducing film disposed on and in direct contact with material ofthe source structure and the drain structure to reduce resistance of thequantum well channel by imparting a tensile or compressive strain on thequantum well channel, wherein the quantum well channel is disposedbetween the strain-inducing film and the semiconductor substrate.
 2. Theapparatus of claim 1, wherein the strain-inducing film is planar.
 3. Theapparatus of claim 2, wherein the strain-inducing film comprises anamorphous material.
 4. The apparatus of claim 3, wherein thestrain-inducing film comprises silicon oxide or silicon nitride.
 5. Theapparatus of claim 1, wherein: the strain-inducing film is configured toimpart a tensile strain on the quantum well channel to increase avelocity of mobile charge carriers in the quantum well channel, themobile charge carriers being electrons; and the quantum well channel isa channel of an N-type device.
 6. The apparatus of claim 1, wherein: thestrain-inducing film is configured to impart a compressive strain on thequantum well channel to increase a velocity of mobile charge carriers inthe quantum well channel, the mobile charge carriers being holes; andthe quantum well channel is a channel of a P-type device.
 7. Theapparatus of claim 1, wherein: the quantum well channel comprises afirst material having a first lattice constant; the source structure andthe drain structure comprise a second material having a second latticeconstant that is different than the first lattice constant; and materialof the quantum well channel does not extend into the source structure.8. The apparatus of claim 7, wherein: the source structure isepitaxially coupled to the quantum well channel to form aheterojunction; the drain structure is epitaxially coupled to thequantum well channel to form another heterojunction; and the quantumwell channel, the source structure, and the drain structure comprise agroup III-V semiconductor, or a group II-VI semiconductor, orcombinations thereof.
 9. The apparatus of claim 1, wherein the quantumwell channel is a channel of a horizontal field-effect transistor; andwherein the horizontal field-effect transistor is a high electronmobility transistor (HEMT).
 10. The apparatus of claim 1, furthercomprising: a contact layer coupled with the quantum well channel,wherein the quantum well channel is disposed between the contact layerand the semiconductor substrate and the strain-inducing layer is indirect contact with the contact layer.
 11. The apparatus of claim 10,further comprising: a first barrier layer disposed between the quantumwell channel and the semiconductor substrate; and a second barrier layerdisposed between the contact layer and the quantum well channel, whereinthe first barrier layer comprises a material having a bandgap energythat is greater than a bandgap energy of the quantum well channel; andthe second barrier layer comprises a material having a bandgap energythat is greater than the bandgap energy of the quantum well channel. 12.The apparatus of claim 11, further comprising one or more buffer layersepitaxially coupled to the semiconductor substrate, the first barrierlayer being epitaxially coupled to the one or more buffer layers. 13.The apparatus of claim 11, wherein: the semiconductor substratecomprises silicon (Si), the first barrier layer comprises indiumaluminum arsenide (InAlAs), or indium phosphide (InP), or combinationsthereof, the quantum well channel comprises indium gallium arsenide(InGaAs), the source structure and the drain structure comprise galliumarsenide (GaAs), the second barrier layer comprises indium aluminumarsenide (InAlAs), or indium phosphide (InP), or combinations thereof,and the contact layer comprises indium gallium arsenide (InGaAs).
 14. Amethod comprising: forming a semiconductor heterostructure comprising: asemiconductor substrate, and a quantum well channel coupled with thesemiconductor substrate; forming a source structure coupled with thequantum well channel and a drain structure coupled with the quantum wellchannel; and depositing a strain-inducing film on and in direct contactwith material of the source structure and the drain structure to reduceresistance of the quantum well channel by imparting a tensile orcompressive strain on the quantum well channel, wherein the quantum wellchannel is disposed between the strain-inducing film and thesemiconductor substrate.
 15. The method of claim 14, wherein depositingthe strain-inducing film comprises depositing an amorphous material. 16.The method of claim 14, wherein depositing the strain-inducing filmprovides a planar strain-inducing film.
 17. The method of claim 14,wherein depositing the strain-inducing film comprises blanket-depositingsilicon oxide or silicon nitride by plasma-enhanced chemical vapordeposition (PECVD) or low pressure chemical vapor deposition (LPCVD).18. The method of claim 14, wherein subsequent to depositing thestrain-inducing film, the strain-inducing film transfers strain to thequantum channel in a process of relaxing.
 19. The method of claim 14,wherein: forming the semiconductor heterostructure further comprisesdepositing a contact layer on the quantum well channel; and thestrain-inducing layer is in direct contact with the contact layer.